RDNA 5 explained: what AMD's next architecture actually changes
AMD has announced nothing yet about RDNA 5. We separate a real architecture from the spec list the leak mill circulates, and the arithmetic underneath it.
Vlad Makarovreviewed and published
AMD has published nothing about RDNA 5 as a consumer graphics architecture. No briefing, no white paper, no product page, no first-party benchmark — the entire public record is one YouTube video from August 21 and the articles that repeated it. That has not stopped "RDNA 5" from becoming the label glued to a spec list with 200 compute units and a 512-bit bus. The more useful question is narrower than the hype: how much of what the leak describes is actually an architecture, and how much is the last one with the dials turned up?
Nothing has been announced
Nothing, at least not by AMD. The company's desktop line is still RDNA 4, shipping since March 2025, with no roadmap entry, architecture disclosure or benchmark for a successor. Every RDNA 5 number in circulation traces to a single Moore's Law is Dead video published on August 21, 2026, which GameGPU summarised the next day. The compute-unit count, the memory configuration, the price range and the ray-tracing comparison all come from it. Two outlets repeating one unreleased video are not two sources. That matters more for an architecture explainer than a launch story: architecture claims arrive with documentation, and here there is none.
The rumour trail, and where it bends
The chain is short enough to follow. The August video seeded the framing; GameGPU's August piece carried the price leaks; Sportskeeda compressed the same material in September into a 30-60% headline; GameGPU returned on September 19 with a scaling analysis that puts the raster gain at 15-25%. Each retelling adjusts the one before it. Sportskeeda attributes its larger number to "a report published on GameGPU," and the only GameGPU article on the card that existed when it was written contains no percentage at all. That is the ordinary behaviour of a spec mill: one claim, several retellings, a headline that grows with each hop.
A spec list is not an architecture
An architecture is the part of a GPU that holds still across a product line: the instruction set, the shape of a compute unit, the cache hierarchy, how work is scheduled and dispatched, and what the fixed-function blocks — geometry, media, ray tracing, matrix — can do. RDNA 2 added the Infinity Cache and a ray accelerator per compute unit. RDNA 3 split the die into chiplets and redesigned the compute unit for dual-issue. RDNA 4 reworked ray tracing and the machine-learning path.
The RDNA 5 leak carries almost none of it. What it carries is a configuration: more compute units, a wider bus, more cache, higher clocks, a smaller node. Those are the dials you turn after the architecture is settled, and they are the easiest figures to invent because they are arithmetic rather than engineering. The genuinely architectural questions — does RDNA 5 keep the 64-stream-processor compute unit, does ray tracing move off the fixed-function units, what replaces the Infinity Cache — are the ones no leak answers.
The leaked configuration, in numbers
| Leaked RDNA 5 specification | Figure |
|---|---|
| Process | 3 nm |
| Compute units | up to 200 |
| Stream processors per CU | 64 |
| Shader cores | 12,800 ALUs |
| Clocks | 3.1-3.4 GHz |
| Memory bus | 512-bit (384-bit also floated) |
| Memory | up to 48 GB GDDR7 |
| Board power | 350-450 W |
Read the table as a scale-up rather than a redesign. 200 compute units at 64 stream processors each is 12,800 shader cores, a large count for Radeon and still fewer than the RTX 5090's 21,760 FP32 cores; the leaked clocks are what close some of that distance. The 3 nm node is the same class Nvidia's Blackwell uses. A 512-bit bus and up to 48 GB of GDDR7 would be firsts for a consumer Radeon, and they are the two claims that would change what the card can run rather than how fast it runs. None of it describes a pipeline, and nothing in the leak says what changed inside the chip.
The arithmetic under the headline
Run the leaked configuration through the standard formula and the architecture's problem shows up in a single line. 12,800 ALUs at two floating-point operations per clock and 3.1-3.4 GHz is roughly 79-87 TFLOPS of FP32. The RTX 5090's 104.8 TFLOPS comes from 21,760 CUDA cores at 2.41 GHz. On the paper number, the next Radeon flagship lands below the Nvidia card it is meant to beat, which is why the advantage case leans on raster efficiency and cache rather than throughput. We set the same figures against the RTX 5090 in September, and they do not resolve in AMD's favour. If RDNA 5 were a genuinely new architecture, that gap is exactly where a real explanation would live. The leak offers more units instead.
The leak mill cannot agree on the product
The clearest sign that none of this is settled architecture reporting is that the sources describing it disagree about what is being built. VideoCardz reported in June that AMD board partners expect RDNA 5 gaming GPUs in mid-to-late 2027, a window TweakTown repeated in September from a separate leak. That reporting names a flagship with 154 compute units, 36 GB of GDDR7 and a 384-bit bus, an RX 10900 XT. The other stream, the one behind the 200-CU RX 10800 XT, describes a different card. Two rumour chains about the same architecture, hundreds of units apart on the configuration at its centre. The spec roundup keeps both threads side by side and they still do not meet, which the earlier leak write-up reached from the other direction.
Ray tracing is the test an architecture has to pass
Ray tracing is where a redesign shows, because it is the workload least improved by adding compute units. GameGPU's own account puts AMD at rough parity with the RTX 5090 in hybrid ray tracing and 35-50% behind in path tracing. Rough parity, on a card with fewer shader cores and an undescribed ray pipeline, is not evidence of an architectural breakthrough. It is evidence of a card matching on the workload where bandwidth and cache help, and losing on the one where dedicated hardware decides. If RDNA 5 had reworked its ray accelerators the way RDNA 4 did, this is the number that would show it. The leak does not carry one.
What would settle it
Four things, and none of them is another leak. AMD's own architecture disclosure, which for RDNA 2, 3 and 4 arrived as a documented pipeline. A retail card with a price. Third-party benchmarks on shipping silicon, measured in frames rather than compute units. And an independent teardown that names the blocks. Until then "RDNA 5" labels a rumoured configuration and an expected launch window, not a described architecture. Every spec table in circulation is a plausible shopping list for a product AMD has not designed in public.
